In integrated circuit design, cells (also referred to as library elements) typically represent a set of devices with specific features and the interconnect structure(s) that connect those devices. An exemplary cell, such as a memory or other type of cell, may include a group of one or more multi-fin (e.g., two semiconductor fins) P-type FINFETs; a group of one or more multi-fin (e.g., two semiconductor fins) N-type FINFETs; at least one metal gate that is patterned over the parallel semiconductor fins of adjacent P-type and N-type FINFETs and subsequently cut into discrete gate sections above an isolation region in an area between the adjacent P-type and N-type FINFETs; and gate contacts landing on ends of the discrete gate sections also above the isolation region in the area between the adjacent P-type and N-type FINFETs. Those skilled in the art will recognize that multiple semiconductor fins are typically incorporated into FINFETs in order to provide increased drive current over conventional single-fin FINFETs. Unfortunately, with cell size scaling and, particularly, cell height scaling (as measured in a direction parallel to the gate sections and perpendicular to the semiconductor fins) critical design rules such as the minimum gate contact to fin distance, the minimum gate cut to fin distance and the minimum distance between fins of P-type and N-type FINFETs may be violated. Violation of these rules can lead to defects and, thereby failures. For example, violation of the minimum gate contact to fin distance can lead to a short between the gate contact and a metal plug that lands on the source/drain region of a semiconductor fin (unless additional features are incorporated into the structure to prevent such shorts). Additionally, violation of the minimum gate cut to fin distance can result in the thickness of the gate on one side of a channel region being too thin, which can, in turn, lead to threshold voltage variations.